The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a nonvolatile memory device.
A NAND-type flash memory device, i.e., a nonvolatile memory device, comprises a unit string including a plurality of cells coupled in series for a large scale of integration. Applicable fields of the NAND-type flash memory device are extending to replace memory sticks, universal serial bus (USB) drivers, and hard disks.
Currently, when fabricating the NAND-type flash memory device, a method for forming a floating gate uses an advanced self aligned-shallow trench isolation (ASA-STI) process because of a decrease in an overlay margin between an active region and the floating gate.
FIGS. 1A to 1E illustrate cross-sectional views of a typical ASA-STI process.
Referring to FIG. 1A, a tunneling insulation layer 101 and a first conductive layer 102 for forming a floating gate are formed over a substrate 100.
Referring to FIG. 1B, portions of the tunneling insulation layer 101, the first conductive layer 102, and the substrate 100 are etched to form trenches 103. Accordingly, an active region in a line shape is defined. Thus, a patterned tunneling insulation layer 101A, a patterned first conductive layer 102A, and a patterned substrate 100A are formed.
Referring to FIG. 5C, an isolation structure 104 is filled in the trenches 103 (FIG. 1B).
Referring to FIG. 1D, the isolation structure 104 is recessed to a certain depth to adjust an effective field oxide height (EFH). Thus, a patterned isolation structure 104A is formed. The EFH refers to a distance from a top surface of the active region defined by the patterned isolation structure 104A to a dielectric layer 105 (FIG. 1E) to be formed by a subsequent process.
As shown in FIG. 1E, the dielectric layer 105 is formed over the surface profile of the patterned first conductive layer 102A including the patterned isolation structure 104A. A second conductive layer 106 for forming a control gate is formed over the dielectric layer 105.
Although not shown, the second conductive layer 106 for a control gate, the dielectric layer 105, and the patterned first conductive layer 102A are etched in a direction perpendicular to the active region to form the floating gate and the control gate.
In the typical ASA-STI process including the etch process to adjust the EFH as shown in FIG. 1D, a height difference between the patterned isolation structure 104A and the patterned first conductive layer 102A is generated. When the second conductive layer 106 for forming the control gate is formed as shown in FIG. 1E, the height difference in lower layers is mirrored in the conductive layer 106. The height difference causes a height non-uniformity among memory cell gates in a wafer and may have an effect on the etch process for forming the control gate. Also, this height difference is mirrored in upper layers of the control gate and may have an effect on a subsequent process. As a result, device characteristics may be deteriorated.